A comparison of CMOS chip to chip interconnections: vertical optical through-Si links versus high density electrical interconnect

Author

Brooke, Martin ; Jokerst, Nan Marie ; Bond, Steven W. ; Wills, D. Scott

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

2

fYear

1998

fDate

3-4 Dec 1998

Firstpage

186

Abstract

High density (HDI) electrical interconnections and vertical optoelectronic interconnections (OE) through-Si links for 3D computational systems have been modeled, and compared and contrasted in the areas of latency, size, and power dissipation. Based upon STA Roadmap projections, which indicate interconnection as a challenge area for coming generations of electronics, optoelectronics may serve a role in chip to chip interconnections for massively parallel computational systems

Keywords

integrated optoelectronics; optical computing; optical interconnections; parallel architectures; 3D computational systems; CMOS chip to chip interconnections; STA Roadmap projection; chip to chip interconnections; high density electrical interconnect; high density electrical interconnections; massively parallel computational systems; optical computing architecture; through-Si links; vertical optical through-Si links; vertical optoelectronic interconnections; Bonding; Delay; Dielectric substrates; Dielectric thin films; Foundries; Integrated circuit interconnections; Integrated optics; Optical computing; Optical crosstalk; Optical interconnections;

fLanguage

English

Publisher

ieee

Conference_Titel

Lasers and Electro-Optics Society Annual Meeting, 1998. LEOS '98. IEEE

Conference_Location

Orlando, FL

Print_ISBN

0-7803-4947-4

Type

conf

DOI

10.1109/LEOS.1998.739523

Filename

739523