FPGA Based High Performance Asynchronous ALU Based on Modified 4 Phase Handshaking Protocol with Tapered Buffers

Author

Bhandari, N. ; Chowdhury, S.R.

Author_Institution

Centre for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol. - Hyderabad, Hyderabad, India

fYear

2014

fDate

12-13 Sept. 2014

Firstpage

1

Lastpage

6

Abstract

The paper presents a high performance implementation of asynchronous ALU on FPGA by minimizing the amount of time taken for the execution of instructions. The amount of time taken for the execution have been minimized using a modified version of 4 phase handshaking protocol. The asynchronous design methodology helps to achieve higher flexibility and performance of the arithmetic logic unit. The ALU has been implemented on Xilinx ISE simulator and Spartan 3E family FPGA board.The speed of the computation has been increased to 1.56 times the speed with the previous available asynchronous versions with the help of modified 4-phase handshaking protocol.

Keywords

asynchronous circuits; field programmable gate arrays; integrated circuit design; protocols; ALU; Spartan 3E family FPGA board; Xilinx ISE simulator; arithmetic logic unit; asynchronous design methodology; high performance implementation; modified 4 phase handshaking protocol; tapered buffers; Clocks; Computer architecture; Delays; Field programmable gate arrays; Pipeline processing; Protocols; Standards;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Communications (ICDCCom), 2014 International Conference on

Conference_Location

Ranchi

Type

conf

DOI

10.1109/ICDCCom.2014.7024720

Filename

7024720