Title :
Analysis of a drain-voltage oscillation of MOSFET under high dV/dt UIS condition
Author :
Soneda, Shinya ; Narazaki, Atsushi ; Takahashi, Tetsuo ; Takano, Kazutoyo ; Kido, Shigenori ; Fukada, Yusuke ; Taguchi, Kensuke ; Terashima, Tomohide
Author_Institution :
Power Device Works, Mitsubishi Electr. Corp., Fukuoka, Japan
Abstract :
In this paper, we investigate a mechanism of drain-voltage oscillation of MOSFET under high dV/dt UIS condition by using numerical simulation and experiments. One of the trigger events of the oscillation is found to be the current path switching between the active region and the termination region with close BVDSS characteristics. By optimizing the device parameters to make appropriate the BVDSS balance, avalanche capability is improved over ~ 40%, enabling the oscillation-free turn-off.
Keywords :
MOSFET; numerical analysis; MOSFET; UIS condition; active region; avalanche capability; current path switching; device parameters; drain-voltage oscillation; numerical simulation; oscillation-free turn-off; termination region; trigger events; Numerical simulation; Oscillators; Power MOSFET; Simulation; Switches; Temperature distribution; Avalanche; MOSFET; Oscillation; UIS;
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2012 24th International Symposium on
Conference_Location :
Bruges
Print_ISBN :
978-1-4577-1594-5
Electronic_ISBN :
1943-653X
DOI :
10.1109/ISPSD.2012.6229046
