Hardening a memory cell for low power operation by gate leakage reduction

A single event causing multiple node upsets is a significant phenomenon for CMOS memories; its occurrence is due to the reduced feature size and the lower power supply voltage in the nanoscales. A low power memory cell that utilizes positive ground level voltage to reduce leakage power (requiring two transistors), is considered and two schemes are proposed for hardening. These designs require 4 additional transistors for hardening, thus they are 12T. The addition of two transistors to reduce the gate leakage is also applied to the DICE cell for comparison purposes (thus making it a 14T scheme for low power operation). A comprehensive simulation based assessment of the performance of these low power cells is pursued under different feature sizes and values of the (virtual) ground level voltage. Figures of merit for performance such as power dissipation, write/read times and static noise margin (SNM) are reported as well as the charge plot of the critical node pair (for tolerance to a single event with single/multiple node upset).