Optimal choice of arithmetic compactors for mixed-signal systems

Compaction circuits that have been used for mixed-signal systems testing constitute a part of encoding/decoding device for an arithmetic error-control code (ECC). These circuits are commonly referred to as residue computing circuits (RCCs). As ECCs originated primarily to protect data transfers over binary channels, their design methodology has been mostly oriented towards a binary case. A non-binary design technique has only been considered for a special type of compaction modulus. In this work, we consider a design technique for a multiple-bit arithmetic compaction circuit with an arbitrary compaction modulus. It is assumed that the data being compacted are fuzzy. This in turn distorts the result of compaction increasing the aliasing rate. Even though the fault free system´s distortion is small, the compaction circuit may aggravate it beyond the acceptable levels making the method impractical. We design a low cost compactor that does not increase the distortion. The circuit can be used for off-line and on-line mixed-signal testing, as well as fault-tolerant data processing and noise-tolerant data transmission.