Improving small-delay fault coverage for on-chip delay measurement

In recent, with the nanometer-scale size, high density, and high frequency of VLSI, the reliability of VLSI is declined by the small-delay defects which are hard to be detected by traditional delay fault testing. As a method for detecting small-delay faults, on-chip delay measurement was proposed, which measures the delay time of paths on Circuit Under Test (CUT). However, if the Path Under Measurement (PUM) outputs a hazard, an incorrect stop signal will be generated. The incorrect stop signal can cause false error indications or test escapes. Therefore, when using on-chip measurement method to detect small-delay defects, single-path sensitization test pattern generation is required. Due to this constraint, the fault coverage is very low. This paper introduces techniques for improving fault coverage, which use multi-scan enable and test point insertion. Evaluation results indicate that for Launch On Shift (LOS) testing with single-path sensitization, by combination on these techniques, we can get an acceptable fault coverage. Specifically, fault coverage are improved 29.77-47.99% by 11.87-40.45% of hardware overhead.