DocumentCode
2479865
Title
Power-sensitive multithreaded architecture
Author
Seng, John S. ; Tullsen, Dean M. ; Cai, George Z N
Author_Institution
Dept. of Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA
fYear
2012
fDate
Sept. 30 2012-Oct. 3 2012
Firstpage
17
Lastpage
24
Abstract
The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-conscious design must therefore go beyond technology and low-level design, but also change the way modern processors are architected. A multithreading processor is attractive in the context of low-power or power-constrained devices for many of the same reasons that enable its high throughput. Primarily, it supplies extra parallelism via multiple threads, allowing the processor to rely much less heavily on speculation. We show that a simultaneous multithreading processor utilizes up to 22% less energy per instruction than a single-threaded architecture. We also explore other power optimizations that are particular to multithreaded architectures, either because they are unavailable to or unreasonable for single-thread architectures.
Keywords
low-power electronics; microprocessor chips; parallel architectures; performance evaluation; power aware computing; high-performance processors; low-level design; low-power devices; microprocessor power consumption; mobile processors; multithreading processor; power optimizations; power-conscious design; power-constrained devices; power-sensitive multithreaded architecture; Benchmark testing; Computer architecture; Instruction sets; Multithreading; Optimization; Power demand;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design (ICCD), 2012 IEEE 30th International Conference on
Conference_Location
Montreal, QC
ISSN
1063-6404
Print_ISBN
978-1-4673-3051-0
Type
conf
DOI
10.1109/ICCD.2012.6378610
Filename
6378610
Link To Document