Automated mixed-signal SoC BIST synthesis utilizing hardware accelerators

BIST techniques for analog and mixed-signal circuits have attracted considerable research activity; especially utilizing on-chip ROMs to store high precision sinusoidal stimuli and pre-calculated Delta-Sigma modulated bit-streams. However, usage of ROMs in high-performance circuits has poses substantial challenges, mainly because of its inability to run at-speed tests and high area overhead due to its prohibitively large size. An alternative to ROM utilization is the use of LFSRs. But, the computation time of the LFSR based BIST synthesis for large mixed-signal SoC poses a huge challenge. A high-performance computing (HPC) based automated mixed-signal SoC BIST synthesis technique that can outperform the conventional ROM implementation not only with respect to the computation time needed to generate the test vectors or waveforms, but also the BIST hardware required, is presented in this paper. Furthermore, the versatility of the presented LFSR based BIST test vector generator, that allows itself to be used for embedding deterministic patterns for LBIST and storing sinusoidal stimuli or pre-calculated Delta-Sigma modulated bit-stream for analog BIST, is demonstrated.