Title :
The performance of hypermesh NoCs in FPGAs
Author :
Marvasti, M. Binesh ; Szymanski, T.H.
Author_Institution :
Dept. of ECE, McMaster Univ., Hamilton, ON, Canada
fDate :
Sept. 30 2012-Oct. 3 2012
Abstract :
We present experimental results for performance of the 2D hypermesh NoC topology, realized with the Altera Family of FPGAs. Hypermeshes are based on the concept of hypergraphs, which consist of a set of nodes and a set of hyper-edges, where the hyper-edges represent low-latency distributed switches. In a 2D hypermesh, the nodes in each row or column are members of a hyperedge, where packets can traverse a hyperedge without encountering router queuing delays. A comparison of the 2D hypermesh, the 2D mesh, and hypercube NoCs is presented. Extensive experimental results show that under the constraint of comparable bisection bandwidth, the 2D hypermesh outperforms the other graph-based network topologies.
Keywords :
delays; field programmable gate arrays; graph theory; hypercube networks; logic design; network routing; network topology; network-on-chip; switching networks; 2D hypermesh NoC topology; 2D mesh; Altera Family; FPGA; bisection bandwidth; graph-based network topology; hypercube NoC; hyperedge; hypergraph; hypermesh NoC performance; low-latency distributed switch; router queuing delay; Bandwidth; Delay; Field programmable gate arrays; Hypercubes; Network topology; Topology;
Conference_Titel :
Computer Design (ICCD), 2012 IEEE 30th International Conference on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-3051-0
DOI :
10.1109/ICCD.2012.6378689
