Title :
High-performance adaptive decision feedback equalizer based on predictive parallel branch slicer scheme
Author :
Yang, Meng-Da ; Wu, An-Yeu Andy
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
Among the existing works of high-speed pipelined Adaptive Decision Feedback Equalizer (ADFE), the pipelined ADFE using the relaxed look-ahead technique results in a substantial hardware saving than the parallel processing or Look-ahead approaches. However, it suffers from both the SNR degradation and slow convergence rate. In this paper, we employ the Predictive Parallel Branch Slicer (PPBS) to eliminate the dependencies of the present and past decisions so as to reduce the iteration bound of Decision Feedback Loop of the ADFE. By adding negligible hardware complexity overheads, the proposed architecture can help to improve the output Mean-square-error (MSE) of the ADFE compared with the Relaxed Look-ahead ADFE architecture. Moreover, we show the superior performance of the proposed pipelined ADFE by theoretical derivations and computer simulation results.
Keywords :
VLSI; adaptive equalisers; convergence; decision feedback equalisers; digital signal processing chips; mean square error methods; pipeline processing; adaptive DFE; adaptive decision feedback equalizer; convergence rate; high-speed pipelined DFE; low-cost VLSI design; output MSE; output mean-square-error; predictive parallel branch slicer scheme; Computer architecture; Computer simulation; Convergence; Decision feedback equalizers; Degradation; Feedback loop; Field-flow fractionation; Hardware; Least squares approximation; Pipeline processing;
Conference_Titel :
Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on
Print_ISBN :
0-7803-7587-4
DOI :
10.1109/SIPS.2002.1049696