Title :
A 54 Mbps (3,6)-regular FPGA LDPC decoder
Author :
Zhang, Tong ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., USA
Abstract :
Applying a joint code and decoder design methodology, we develop a high-speed (3, k)-regular LDPC code partly parallel decoder architecture, based on which a 9216-bit, rate-1/2 (3,6)-regular LDPC code decoder is implemented on an Xilinx FPGA device. When performing maximum 18 iterations for each code block decoding, this partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10-6 at 2 dB over an AWGN channel.
Keywords :
AWGN channels; decoding; digital signal processing chips; error statistics; field programmable gate arrays; parallel architectures; 54 Mbit/s; AWGN channel; BER; DSP; FPGA LDPC decoder; Xilinx FPGA device; bit error rate; high-speed decoder architecture; joint code/decoder design methodology; low-density parity check code; partly parallel decoder architecture; AWGN channels; Application specific integrated circuits; Bit error rate; Design methodology; Field programmable gate arrays; Hardware; Iterative decoding; Parity check codes; Routing; Throughput;
Conference_Titel :
Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on
Print_ISBN :
0-7803-7587-4
DOI :
10.1109/SIPS.2002.1049697
