A 1.2 μm CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer

Author

Thamsirianunt, Manop ; Kwasniewski, Tadeusz A.

Author_Institution

MITEL Semicond., Kanata, Ont., Canada

fYear

1994

fDate

1-4 May 1994

Firstpage

383

Lastpage

386

Abstract

A single-chip, low-power all CMOS PLL frequency synthesizer for digital mobile radio communication systems is presented. The design of PLL components: VCO, dual-modulus prescaler and phase-frequency detector are discussed. Novel circuit techniques and design methodology allow GHz frequency range operation, and result in good phase noise performance. The measured results of a monolithic 1.2 μm CMOS PLL implementation indicate a frequency range of 800 to 900 MHz with -94 dBc/Hz phase noise at a 1 MHz carrier offset, and a power consumption of 18 mW at 5 volts

Keywords

CMOS integrated circuits; UHF integrated circuits; digital radio; frequency synthesizers; mixed analogue-digital integrated circuits; mobile radio; phase locked loops; radio equipment; 1.2 micron; 18 mW; 5 V; 800 to 900 MHz; CMOS implementation; PLL frequency synthesizer; UHF type; VCO; digital radio communication systems; dual-modulus prescaler; low-power operation; mobile RF synthesizer; monolithic PLL implementation; phase noise performance; phase-frequency detector; single-chip type; Design methodology; Frequency synthesizers; Land mobile radio; Phase detection; Phase frequency detector; Phase locked loops; Phase noise; Power measurement; Radiofrequency integrated circuits; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379683

Filename

379683