A 1.2 GIP general purpose digital image processor

Author

Evans, Stephen ; Walker, Simon ; Thacker, Neil A. ; Yates, Rob B. ; Ivey, Peter A.

Author_Institution

Dept. of Electron. & Electr. Eng., Sheffield Univ., UK

fYear

1994

fDate

1-4 May 1994

Firstpage

99

Lastpage

102

Abstract

In this paper we present a new processor (DIP chip) for image compression which combines principles of multi-pipeline and array processing. The device is not specific to any one image compression algorithm, and can be regarded as a general purpose processor. The main aim of this paper is to describe our solutions to problems associated with the large bandwidth required, for both image data and instruction streams. We also address the necessary problem of increasing the array clock frequency relative to the input/output clock frequency without the need for a large on chip instruction cache, or fast external clock speeds

Keywords

CMOS digital integrated circuits; data compression; digital signal processing chips; image coding; image processing equipment; parallel architectures; pipeline processing; reduced instruction set computing; 1.2 GIPS; RISC; array clock frequency; array processing; bandwidth; digital image processor; general purpose processor; image compression; multipipeline processing; Bandwidth; Clocks; Digital images; Frequency; Image coding; Image processing; Pipelines; Read-write memory; Reduced instruction set computing; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379758

Filename

379758