A 50 MHz 70 mW 8-tap adaptive equalizer/Viterbi sequence detector in 1.2 μm CMOS

Author

Uehara, Gregory T. ; Wong, Caesar S H ; Rudell, Jacques C. ; Gray, Paul R.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1994

fDate

1-4 May 1994

Firstpage

51

Lastpage

54

Abstract

A new architecture for digital implementation of the adaptive equalizer in Class IV Partial Response Maximum Likelihood (PRML) channels employing parallelism and pipelining is described. The architecture was used in a prototype integrated circuit in a 1.2 μm CMOS technology to implement a 50 MHz adaptive equalizer and Viterbi sequence detector dissipating 70 mW from a 3.3 V supply

Keywords

CMOS digital integrated circuits; Viterbi detection; adaptive equalisers; detector circuits; hard discs; partial response channels; pipeline processing; 1.2 micron; 3.3 V; 50 MHz; 70 mW; CMOS; Class IV partial response maximum likelihood; PRML channels; Viterbi sequence detector; adaptive equalizer; digital implementation; disk drive channels; parallelism; pipelining; Adaptive equalizers; Adaptive filters; Clocks; Delay; Detectors; Error correction; Finite impulse response filter; Least squares approximation; Pipeline processing; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379768

Filename

379768