DocumentCode
2492230
Title
Power-Delay Optimized Design of Cascaded ECL Gates
Author
Grasso, A.D. ; Palumbo, G. ; Alioto, M.
Author_Institution
Dipt. di Ingegneria Elettrica, Elettronica e dei Sistemi, Catania Univ.
fYear
0
fDate
0-0 0
Firstpage
233
Lastpage
236
Abstract
In this paper a design methodology to design low-power cascaded ECL gates is developed. The results can be applied when a power constraint is assigned, and the available current per gate is much lower than the value which minimizes the propagation delay. The strategy is process independent and is simple enough for hand calculations, avoiding the time-consuming approach based on iterative simulations. A design example based on a 20 GHz bipolar process is introduced to validate the procedure
Keywords
cascade networks; emitter-coupled logic; logic design; logic gates; low-power electronics; 20 GHz; bipolar process; cascaded ECL gates; iterative simulations; power-delay optimized design; propagation delay; Capacitance; Circuits; Design methodology; Design optimization; Energy consumption; Iterative methods; Logic design; Minimization; Propagation delay; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Research in Microelectronics and Electronics 2006, Ph. D.
Conference_Location
Otranto
Print_ISBN
1-4244-0157-7
Type
conf
DOI
10.1109/RME.2006.1689939
Filename
1689939
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