High-Level Decision Diagram based Fault Models for Targeting FSMs

Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern generation. Those methods have proven efficient. However, all of them target modules inside the datapath of the circuit. In this paper, we show by experiments that the fault coverage achieved by full datapath tests is often lower than what can be achieved if faults in the control part FSM were additionally considered. We also propose a new type of fault model for targeting faults in FSMs embedded to RTL descriptions. In addition, we present an alternative for traditional assignment decision diagrams, which provides for a more general representation of RTL circuits. We show that our model, called high-level decision diagrams, allows efficient high-level test path activation. According to experiments the proposed approach outperforms state-of-the-art test pattern generation tools