On a Hardware Implementing Method of the Optimized AES Encryption Algorithm

This paper introduces the principle of AES encryption algorithm and gives a detailed description of the algorithm FPGA design and implementation. The limitation of the current AES implementation methods is that the thruput is small. In allusion to this problem, this paper applies assembly-line technology in the designation and gains the best optimized area and speed. It implements AES encryption algorithm in hardware description language. Finally, the design is downloaded to the FPGA chip CycloneII EP2C35F672 to check. The experiment results show that even under the circumstance of the low global clock frequency, it can obtain high thruput.