DocumentCode :
2496067
Title :
MICA: a mapped interconnection-cached architecture
Author :
Lyuu, Yuh-Dauh ; Schenfeld, Eugen
Author_Institution :
NEC Res. Inst., Princeton, NJ, USA
fYear :
1995
fDate :
6-9 Feb 1995
Firstpage :
80
Lastpage :
89
Abstract :
MICA (Mapped Interconnection-Cached Architecture) is a novel architecture combining large reconfigurable networks and small, fast on-line routing, crossbar switches. It offers a good match for parallel applications exhibiting switching locality. Switching locality means that the need to “switch” or route the information to or from each PE is limited to a small set of sources or destinations. A parallel programming paradigm to attempt and minimize the movement of information by reconfiguring the relative proximity of the PEs is introduced. We aim to complete most communication requests with only two levels of routing decisions among a small set of channels. Multi-hop routing is not used as often, resulting in better performance
Keywords :
cache storage; multiprocessor interconnection networks; parallel programming; performance evaluation; MICA; crossbar switches; mapped interconnection-cached architecture; multi-hop routing; on-line routing; parallel applications; parallel programming paradigm; reconfigurable networks; relative proximity; Concurrent computing; Hypercubes; Interference; National electric code; Parallel architectures; Parallel programming; Routing; Switches; Technological innovation; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Frontiers of Massively Parallel Computation, 1995. Proceedings. Frontiers '95., Fifth Symposium on the
Conference_Location :
McLean, VA
Print_ISBN :
0-8186-6965-9
Type :
conf
DOI :
10.1109/FMPC.1995.380460
Filename :
380460
Link To Document :
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