The application of low power dissipation and reconfigurable technology on SoC cache

The static power dissipation is account for a small part compared to the high overturn dissipation among clock dissipation. So the clock dissipation optimization is mainly aimed at the dynamic dissipation optimization. This paper puts forward a low power dissipation and Reconfigurable technology aimed at SoC cache according to the architecture of the MIPS patch memory system and its work principle. It goes into particulars on software and hardware methods and gives the experiment results compared to the traditional method.