Diagnosis of single gate delay faults in combinational circuits using delay fault simulation

In this paper, we propose a method of diagnosing gate delay faults using delay fault simulation. In the method, suspected faults are deduced by fault simulation and backward path-tracing using diagnostic test-pairs with observed faulty responses. Also, by fault simulation using diagnostic test-pairs with fault-free responses, non-existent faults are deduced, and they are removed from the set of suspected faults. Finally, we present experimental results on the ISCAS´85 benchmark circuits. The experimental results show that by simple processes of backward path-tracing and fault simulation, this method achieves reasonable diagnostic resolutions in a short time