Comparative stress analysis of an innovative package with embedded die substrate

Continuous integrated circuit (IC) package downsizing with increasing function integration have being the major evolving paths in the semiconductor industry for decades. As present packaging technologies such as lead-frame, wire bond ball grid array (BGA), and flip-chip BGA are approaching their limit gradually. An alternative new structure, the embedded technology is thus becoming one of potential solution for further downsizing and function integration while struggling among cost, performance, and size challenges. Embedded component(s) inside the substrate not only release the space on top surface and could reduce the form factor, at the same time. It could also provides the shortest routing path between components for electrical performance and reduce total cost from system point of view. In this paper, we report an innovative package structure, which is a system-in-package with an embedded die substrate. First die is embedded in the center of the substrate to form an symmetrical structure, while the second die is flipped on top of the substrate. Stress simulation result from various structures: embedded die substrate, flip chip package and flip chip on embedded die substrate are analyzed to predict the behavior under thermal and stress condition. Corresponding Shadow Moire analysis for each structure is also included. Failure mode in the innovative package structure with structural experience precondition test will be presented and discussed.