High density assembly technology using stacking method

We have developed a new 3-dimensional (3D) Wafer-to-Wafer stacking technology in which each wafer was stacked one after another, using a unique Through Silicon Via (TSV) fabricated by wet etching technology and surface-micro bump on the lower wafer. Our Wafer-to-Wafer stacking method use a direct connection between backside TSVs of an upper wafer and micro-bumps of a lower wafer. This interconnection method is useful that all back-side processes are removed except wafer thinning, and also total stacking process is simplified and shortened. Each wafer is fabricated by using 0.18 um CMOS technology based on 8-inch wafers. Electrical connection between each wafer was almost 100% and interconnection resistance less than 0.7Omega between a TSV of the upper wafer and a micro-bump of lower wafer. Five prototype devices showed sophisticated functionality, and yield in the stacked wafer was over 60%.