DocumentCode
2497375
Title
BISTing switched-current circuits
Author
Renovell, M. ; Azaïs, F. ; Bodin, J.C. ; Bertrand, Y.
Author_Institution
Univ. des Sci. et Tech. du Languedoc, Montpellier, France
fYear
1998
fDate
2-4 Dec 1998
Firstpage
372
Lastpage
377
Abstract
In this paper, a BIST scheme is proposed that applies to any kind of SI building blocks constituted of an aggregate of identical memory cells. The fundamental idea is to reconfigure the building block into a cascade of memory cells so that the output current is equal in magnitude to the input current. Using a very simple circuitry, an error current can then easily be generated that permits one to detect faults in the block
Keywords
analogue integrated circuits; analogue processing circuits; analogue storage; built-in self test; fault location; integrated circuit testing; integrating circuits; switched current circuits; BIST scheme; SI building blocks; SI integrator; SI memory cells; error current; fault detection; memory cell cascade; switched-current circuits; Aggregates; Built-in self-test; Capacitors; Circuit testing; Clocks; Integrated circuit interconnections; MOS devices; MOSFETs; Output feedback; Rain; Robots; Silicon compounds; Switches; Switching circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
ISSN
1081-7735
Print_ISBN
0-8186-8277-9
Type
conf
DOI
10.1109/ATS.1998.741641
Filename
741641
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