• DocumentCode
    2497628
  • Title

    Partitioning and reordering techniques for static test sequence compaction of sequential circuits

  • Author

    Hsiao, Michael S. ; Chakradhar, Srimat T.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
  • fYear
    1998
  • fDate
    2-4 Dec 1998
  • Firstpage
    452
  • Lastpage
    457
  • Abstract
    We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: (1) fault-list and test-set partitioning, and (2) vector re-ordering. Typically, the first few vectors of a test set detect a large number of faults. The remaining vectors usually constitute a large fraction of the test set, but these vectors ore included to detect relatively few hard faults. We show that significant compaction can be achieved by partitioning faults into hard and easy faults. This significantly reduces the computational cost for static test set compaction without affecting quality of compaction. The second technique re-orders vectors in a test yet by moving sequences that detect hard faults to the beginning of the test set. Fault simulation of the newly concatenated re-ordered test set results in the omission of several vectors so that the compact test set is smaller than the original test set. Experiments on several ISCAS 89 sequential benchmark circuits and large production circuits show that our compaction procedure yields significant test set reductions in low execution times
  • Keywords
    automatic test pattern generation; fault simulation; logic testing; sequential circuits; vectors; ATPG; computational cost reduction; concatenated re-ordered test set; fault coverage curves; fault simulation; fault-list partitioning; low execution times; partitioning techniques; reordering techniques; sequential circuits; static test sequence compaction; test set compaction method; test-set partitioning; vector re-ordering; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Compaction; Computational efficiency; Computational modeling; Concatenated codes; Electrical fault detection; Fault detection;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
  • ISSN
    1081-7735
  • Print_ISBN
    0-8186-8277-9
  • Type

    conf

  • DOI
    10.1109/ATS.1998.741656
  • Filename
    741656