Generating test patterns for fault detection in combinational circuits using genetic algorithm

Author

Baid, Akash ; SRIVASTAVA, ANURAG K.

Author_Institution

Dept. of Electron. & Commun. Eng., Jaypee Inst. of Inf. Technol., Noida, India

fYear

2013

fDate

12-14 April 2013

Firstpage

1

Lastpage

4

Abstract

In this paper we propose a method for the automatic test pattern generation for detecting stuck-at-faults in combinational VLSI circuits using genetic algorithm (GA). Derivation of minimal test sets helps to reduce the post-production cost of testing combinational circuits. The GA proves to be an effective algorithm in finding optimum number of test patterns from the highly complex problem space. In this paper results are obtained for single stuck-at-fault in the ISCAS 1989(C17) benchmark circuit.

Keywords

VLSI; automatic test pattern generation; circuit optimisation; combinational circuits; fault diagnosis; genetic algorithms; logic testing; GA; automatic test pattern generation; combinational VLSI circuit; combinational circuit testing; genetic algorithm; minimal test set; post-production cost; stuck-at-fault detection; Biological cells; Circuit faults; Combinational circuits; Fault detection; Genetic algorithms; Integrated circuit modeling; Very large scale integration; genetic algorithm; stuck-at-faults; test pattern generation;

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering and Systems (SCES), 2013 Students Conference on

Conference_Location

Allahabad

Print_ISBN

978-1-4673-5628-2

Type

conf

DOI

10.1109/SCES.2013.6547506

Filename

6547506