Low-Latency, Low-Area Overhead and High Throughput NoC Architecture for FPGA Based Computing System

A network on Chip (NoC) is the interconnection platform that answers the requirements of modern on-Chip design. In this paper we describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works. The architecture has been optimized for Xilinx FPGAs and the NoC is capable of operating at a frequency of 305.573 MHz in a Virtex-5 xc5vlx110t-3-ff1136 FPGA. We have also developed a bridge so that generic Wishbone bus compatible IP blocks can be connected to the NoC.