DocumentCode
249794
Title
Design of Phase Frequency Detector and Charge Pump for Low Voltage High Frequency PLL
Author
Kailuke, Aniruddha C. ; Agrawal, Pulin ; Kshirsagar, R.V.
Author_Institution
Dept. of Electron. & Commun. Eng., P.I.E.T., Nagpur, India
fYear
2014
fDate
9-11 Jan. 2014
Firstpage
74
Lastpage
78
Abstract
A simple new phase frequency detector and integrated Dickson Charge pump design with charge transfer switches (CTS´s) are presented in this paper. The proposed Phase-Frequency Detector (PFD) and Charge-Pump are useful for low voltage, high frequency Phase-Looked-loops (PLL). This brief analyzes the blind zone in latch-based PFDs and proposes a technique that removes the blind zone caused by the precharge time of the internal nodes. With the proposed technique, the PFD achieves a small dead zone. The experimental results shows that the proposed PFD has minimal dead zone compared with the conventional PFD and CTS based Dickson charge pump is the best structure for integration. The PFD and Charge Pump are designed and simulated on Tanner 13.0V tool and has been simulated in a 0.18μm CMOS technology.
Keywords
CMOS integrated circuits; charge pump circuits; phase detectors; phase locked loops; CMOS technology; CTS; charge transfer switches; integrated Dickson charge pump design; latch-based PFD; low voltage high frequency PLL; minimal dead zone; phase frequency detector; Capacitors; Charge pumps; Charge transfer; Clocks; Logic gates; Phase frequency detector; Phase locked loops; Charge Pump (CP); Dead Zone; Phase Frequency Detector (PFD); Phase lock loop (PLL);
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Systems, Signal Processing and Computing Technologies (ICESC), 2014 International Conference on
Conference_Location
Nagpur
Type
conf
DOI
10.1109/ICESC.2014.21
Filename
6745349
Link To Document