FPGA implementation and analysis of random delay insertion countermeasure against DPA

Security devices can reveal critical information about the cryptographic key from the power consumption of their circuits. Differential power analysis (DPA) is one of the most effective power analysis techniques. In recent years numerous countermeasures against the DPA attack of hardware implementations of security algorithms have been proposed. In this paper, we investigate the random delay insertion (RDI) countermeasure. Previous research has evaluated RDI for microprocessor implementations; however, its security properties in relation to hardware implementations have not been investigated in detail. We prove both theoretically and practically that it is an effective technique on FPGA devices and we propose a set of critical parameters that can be utilized to optimize a security algorithm design with RDI in terms of area, speed and power. In this work, we implement the first hardware security architecture with RDI on an FPGA device, and attack it using DPA. It is shown that RDI is an efficient countermeasure technique on FPGA in comparison to other countermeasures.