Title :
The FPGA implement of ADPLL without retimed clock
Author :
Jiang, Shuai ; He, Songbai ; You, Fei
Author_Institution :
Sch. of Electron. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
A modified method to evaluate the phase of all digital phase-locked loop (ADPLL) output signal is proposed in this paper for improving the robustness property of the loop. The reference clock is used throughout the system as the synchronous clock, which can avoid the metastable output and the injection spurs caused by retiming mechanism, and differential units are added to reduce the accumulation of phase error. Besides, a time-digital converter (TDC) based loop shifting flip-flops is proposed to achieve a wide range of operation. The FPGA simulation results show that the error of frequency detector is less than 0.20/00, and the loop get into locking by 12 μs and stable in the condition of FSW=4.8.
Keywords :
digital phase locked loops; field programmable gate arrays; flip-flops; FPGA simulation; all digital phase-locked loop; injection spur avoidance; metastable output avoidance; reference clock; synchronous clock; time 12 mus; time-digital converter based loop shifting flip-flops; Clocks; Field programmable gate arrays; Frequency control; Frequency synthesizers; Phase locked loops; Shift registers; Synchronization; ADPLL; Phase evaluate; Time to digital converter;
Conference_Titel :
Anti-Counterfeiting, Security and Identification (ASID), 2011 IEEE International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-631-6
DOI :
10.1109/ASID.2011.5967442
