ACTion: combining logic synthesis and technology mapping for MUX based FPGAs

Author

Günther, Wolfgang ; Drechsler, Rolf

Author_Institution

Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany

Volume

1

fYear

2000

fDate

2000

Firstpage

130

Abstract

Technology mapping for multiplexor (MUX) based field programmable gate arrays (FPGAs) has widely been considered. A new algorithm is proposed that applies techniques from logic synthesis during mapping. By this, the target technology is considered in the minimization process. Binary decision diagrams (BDDs) are used as an underlying data structure due to the close relation between BDDs and MUX netlists. The algorithm uses local don´t cares obtained by a greedy algorithm. The mapping is sped up by computing signatures. A trade-off quality versus runtime can be specified by the user by setting different parameters. Experimental results comparing the approach to the best known results show improvements of more than 30% for area and 40% for delay for many instances

Keywords

binary decision diagrams; field programmable gate arrays; logic CAD; minimisation; multiplexing; ACTion; MUX based FPGAs; MUX netlists; binary decision diagrams; computing signatures; greedy algorithm; logic synthesis; minimization process; multiplexor based field programmable gate arrays; technology mapping; underlying data structure; Binary decision diagrams; Boolean functions; Circuit synthesis; Computer architecture; Computer science; Data structures; Field programmable gate arrays; Minimization; Network synthesis; Programmable logic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Euromicro Conference, 2000. Proceedings of the 26th

Conference_Location

Maastricht

ISSN

1089-6503

Print_ISBN

0-7695-0780-8

Type

conf

DOI

10.1109/EURMIC.2000.874625

Filename

874625