The impact of recent DRAM architectures on embedded systems performance

Embedded computing systems utilize less cache space and fewer memory hierarchy levels than ordinary PC or workstation systems due to cost, area and power dissipation restrictions. Consequently, they particularly depend on the performance of the underlying dynamic RAM (DRAM) main-memory system. Hence, two recent DRAM architectures, the widely-used synchronous DRAMs (SDRAMs) and the next-generation memory called the Direct Rambus DRAM (RDRAM), are investigated in this paper. Performance gains are revealed that can be achieved by exploiting features of recent memory interfaces with simple enhancements of current embedded memory controllers. Different approaches for memory access schemes are investigated by simulation of the DRAM architectures and the memory controller, together with an out-of-order-issue, superscalar-CPU model running various applications. The simulations lead to the following results: using RDRAMs instead of SDRAMs improves the performance of the system by up to one third, while exploiting the multibank structure of DRAMs improves the performance more than pipelining memory transfers does