• DocumentCode
    2502467
  • Title

    40 Gb/s integrated clock and data recovery circuit in a silicon bipolar technology

  • Author

    Wurzer, M. ; Bock, J. ; Zirwas, W. ; Knapp, H. ; Schumann, F. ; Felder, A. ; Treitinger, L.

  • Author_Institution
    Siemens AG, Munich, Germany
  • fYear
    1998
  • fDate
    27-29 Sep 1998
  • Firstpage
    136
  • Lastpage
    139
  • Abstract
    An integrated clock and data recovery circuit (CDR) applying the PLL technique has been developed for future optical transmission systems. It is fabricated in a 0.5 μm/50 GHz fT double-polysilicon bipolar technology using only production-like process steps. The circuit operates up to 40 Gb/s, which is the highest operating speed to date for this type of IC in a silicon bipolar technology
  • Keywords
    bipolar digital integrated circuits; digital phase locked loops; elemental semiconductors; flip-flops; high-speed integrated circuits; optical communication equipment; silicon; synchronisation; timing circuits; 0.5 micron; 40 Gbit/s; D-flip-flop; PLL technique; Si; Si bipolar technology; double-polysilicon bipolar technology; integrated clock/data recovery circuit; optical transmission systems; Clocks; Delay; Filters; Flip-flops; High speed optical techniques; Integrated circuit technology; Master-slave; Repeaters; Silicon; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Bipolar/BiCMOS Circuits and Technology Meeting, 1998. Proceedings of the 1998
  • Conference_Location
    Minneapolis, MN
  • ISSN
    1088-9299
  • Print_ISBN
    0-7803-4497-9
  • Type

    conf

  • DOI
    10.1109/BIPOL.1998.741905
  • Filename
    741905
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2502467