DocumentCode :
2505368
Title :
Yield of silicon selective epitaxial growth and its role in the production planning and control of three-dimensional semiconductor devices
Author :
Chen, Shannon ; Takoudis, Christos ; Uzsoy, Reha
Author_Institution :
Sch. of Chem. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
1996
fDate :
14-16 Oct 1996
Firstpage :
212
Lastpage :
217
Abstract :
We focus on the yield (Y) and growth rate (G) of silicon selective epitaxial growth (SEG) at 820 to 970°C, and pressures between 40 and 150 Torr. Since the yield of silicon SEG is a potential bottleneck in the manufacture of three-dimensional integrated circuits, e.g., 3-D CMOS, basic knowledge of Y and its dependence on operating conditions, substrate surface parameters, and processing time is of key importance. The conditions investigated include deposition temperature, deposition pressure, SEG thickness, processing time, seed window area, distance between seed windows (local seed window density), and feed composition. The yield is found to improve with higher deposition temperatures, higher HCl feed flows, shorter processing times, higher Cl/H feed ratios, and lower Si/Cl feed ratios. The seed window area and distance between seed windows do not appear to affect the yield at the conditions studied. Growth rate uniformity is observed to improve with lower pressure and temperature, longer processing times, lower HCl feed concentrations, higher Si/Cl feed ratios, and lower Cl/H feed ratios. The implications of these observations for production planning and control of such facilities are discussed
Keywords :
elemental semiconductors; integrated circuit yield; production control; semiconductor epitaxial layers; semiconductor growth; silicon; vapour phase epitaxial growth; 3D CMOS IC; 40 to 150 torr; 820 to 970 C; Si; feed concentration; growth rate; manufacture; production control; production planning; seed window; silicon selective epitaxial growth; three-dimensional semiconductor device; yield; CMOS process; Epitaxial growth; Feeds; Integrated circuit manufacture; Integrated circuit yield; Manufacturing processes; Silicon; Substrates; Temperature; Three-dimensional integrated circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Manufacturing Technology Symposium, 1996., Nineteenth IEEE/CPMT
Conference_Location :
Austin, TX
ISSN :
1089-8190
Print_ISBN :
0-7803-3642-9
Type :
conf
DOI :
10.1109/IEMT.1996.559732
Filename :
559732
Link To Document :
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