Title :
Integrated resynthesis for low power
Author :
Coudert, Olivier ; Haddad, Ramsey
Author_Institution :
Synopsys Inc., Mountain View, CA, USA
Abstract :
Research on synthesis for low power has been done in all three stages of logic synthesis: technology independent optimization, technology mapping, and technology dependent optimization. This paper presents an integrated method, using remapping and technology dependent optimizations, to minimize the power of a mapped circuit under the given delay constraints. It produces 24% savings in power
Keywords :
circuit optimisation; logic design; delay; integrated resynthesis; logic synthesis; low power circuit; power minimization; remapping; technology dependent optimization; technology independent optimization; technology mapping; Circuit synthesis; Constraint optimization; Costs; Delay; Integrated circuit synthesis; Integrated circuit technology; Logic circuits; Logic devices; Power dissipation; Space technology;
Conference_Titel :
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3571-6
DOI :
10.1109/LPE.1996.547501
