Title :
Leap frog multiplier
Author :
Mahant-Shetti, Shivaling S. ; Lemonds, Carl ; Balsara, Poras
Author_Institution :
DSPRDC, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
Array multipliers are popular due to their regular compact structure. Timing analysis of a full adder has resulted in a different array connection pattern that provides improved throughput for the multiplier while reducing its power dissipation from spurious transitions. The paper details the new array design and some results obtained
Keywords :
digital arithmetic; logic arrays; logic design; multiplying circuits; timing; array connection pattern; array design; array multipliers; full adder; leap frog multiplier; power dissipation reduction; spurious transitions; throughput improvement; timing analysis; Adders; Circuits; Delay; Instruments; Latches; Pattern analysis; Power dissipation; Throughput; Timing; Topology;
Conference_Titel :
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3571-6
DOI :
10.1109/LPE.1996.547512
