Title :
Simultaneous buffer and wire sizing for performance and power optimization
Author :
Cong, Jason ; Koh, Cheng-Kok ; Leung, Kwok-Shing
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Abstract :
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions. This relation leads to a polynomial time algorithm for computing the lower and upper bounds of the optimal SBWS solutions, which enables an efficient optimal algorithm for computing optimal SBWS solutions. We have applied the SBWS algorithms to the clock nets in a spread spectrum IF transceiver chip and HSPICE simulations show that our algorithms can reduce skew and power by a factor of 3.5X and 2.6X, respectively, when compared to the manual layout of the clock nets in the original chip
Keywords :
buffer circuits; circuit optimisation; clocks; delays; HSPICE simulation; SBWS algorithm; buffer sizing; clock net; delay minimization; layout; performance optimization; polynomial time; power dissipation minimization; simultaneous buffer and wire sizing; skew; spread spectrum IF transceiver chip; wire sizing; Capacitance measurement; Clocks; Delay effects; Iterative algorithms; Lagrangian functions; Optimization; Power measurement; Routing; Size measurement; Wire;
Conference_Titel :
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3571-6
DOI :
10.1109/LPE.1996.547521
