Title :
Optimization of the gate misalignment effects in graded channel DG FD SOI n-MOSFET with high - κ gate dielectrics
Author :
Sharma, Rupendra Kumar ; Gupta, Mridula ; Gupta, R.S.
Author_Institution :
Dept. of Electron. Sci., Univ. of Delhi South Campus, New Delhi
Abstract :
In this paper, gate misalignment effect have been analyzed in nanoscale double gate (DG) fully depleted (FD) SOI n-MOSFETs, incorporating two important technological issues-graded channel engineering and high-kappa gate dielectrics, using 3-D device simulations. The present work provides a valuable design insight in the performance of nanoscale graded channel DG FD SOI n-MOSFET with high-kappa gate dielectrics incorporating gate misalignment effects and serve as an accurate tool to optimize key device parameters aiding technology development.
Keywords :
MOSFET; high-k dielectric thin films; silicon-on-insulator; 3-D device simulations; gate misalignment; high-kappa gate dielectrics; nanoscale double gate fully depleted SOI n-MOSFETs; Dielectric devices; High K dielectric materials; High-K gate dielectrics; MOSFET circuits; Nanoscale devices; Thickness control; Threshold voltage; Transconductance; Tunneling; Very large scale integration; ATLAS 3-D device simulation; Graded channel; double gate; high-κ gate dielectric;
Conference_Titel :
Recent Advances in Microwave Theory and Applications, 2008. MICROWAVE 2008. International Conference on
Conference_Location :
Jaipur
Print_ISBN :
978-1-4244-2690-4
Electronic_ISBN :
978-1-4244-2691-1
DOI :
10.1109/AMTA.2008.4762977
