Title :
A 800 MHz system-on-chip for wireless infrastructure applications
Author :
Agarwala, Sanjive ; Wiley, Paul ; Rajagopal, Arjun ; Hill, Anthony ; Damodaran, Raguram ; Nardini, Lewis ; Anderson, Tim ; Mullinnix, Steven ; Flores, Jose ; Yue, Heping ; Chachad, Abhijeet ; Apostol, John ; Castille, Kyle ; Narasimha, Usha ; Wolf, Tod ;
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
The 800MHz System-on-Chip implements the C64x VLIW DSP VelociTI.2™ Architecture and delivers 6400 MIPS, 3200 16-bit MMACs, 6400 8-bit MMACs at 0.17 mW/MMAC (8 bit). The chip is implemented in state of the art 90 nm CMOS technology with 7-layer copper metalization. The core dissipates 1080 mW at 800 MHz, 1.2V. The system-on-chip is targeted for high performance wireless infrastructure application. It has an 8-way VLIW DSP core, a 2-level memory system, and an I/O bandwidth of 3.2GB/s.
Keywords :
CMOS integrated circuits; copper; digital signal processing chips; system-on-chip; 0.17 mW; 1.2 V; 1080 mW; 2-level memory system; 7-layer copper metalization; 8-way VLIW DSP core; 800 MHz; 90 nm; C64x VLIW DSP VelociTI.2™ architecture; CMOS technology; Cu; I/O bandwidth; state of the art; system-on-chip; wireless infrastructure applications; Acceleration; Arithmetic; Computer architecture; Decoding; Digital signal processing; Digital signal processing chips; Forward error correction; Registers; System-on-a-chip; VLIW;
Conference_Titel :
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN :
0-7695-2072-3
DOI :
10.1109/ICVD.2004.1260953
