DocumentCode :
2510014
Title :
Static timing analysis of irreversible crosstalk noise pulse faults
Author :
Phadoongsidhi, Marong ; Saluja, Kewal K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
fYear :
2004
fDate :
2004
Firstpage :
437
Lastpage :
442
Abstract :
In a large scale deep sub-micron VLSI design it is impractical to consider all possible aggressor-victim pairs as candidates for crosstalk coupling faults. Inevitably, a significant portion of these crosstalk pairs can be safely discarded from a target faultlist. In this paper, we have developed a static timing analysis technique to identify pairs which can be identified as redundant from crosstalk point of view. Experimental results on ISCAS´89 and ITC´99 benchmark circuits show that our algorithm achieves a reasonable level of crosstalk-induced pulse faultlist reduction without being unduly demanding on computational resources.
Keywords :
VLSI; crosstalk; delay circuits; fault diagnosis; flip-flops; integrated circuit design; noise; timing; benchmark circuits; crosstalk coupling faults; crosstalk noise pulse faults; deep submicron VLSI design; delay circuit; flip flops; static timing analysis; very large scale integrated circuit design; Circuit faults; Circuit testing; Clocks; Coupling circuits; Crosstalk; Delay; Information analysis; Logic design; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN :
0-7695-2072-3
Type :
conf
DOI :
10.1109/ICVD.2004.1260961
Filename :
1260961
Link To Document :
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