DocumentCode
25104
Title
Hexagon DSP: An Architecture Optimized for Mobile Multimedia and Communications
Author
Codrescu, Lucian ; Anderson, Willie ; Venkumanhanti, Suresh ; Mao Zeng ; Plondke, Erich ; Koob, Chris ; Ingle, Atul ; Tabony, Charles ; Maule, Rick
Author_Institution
Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Volume
34
Issue
2
fYear
2014
fDate
Mar.-Apr. 2014
Firstpage
34
Lastpage
43
Abstract
Heterogeneous computing is essential for mobile products to meet power and performance targets. The Qualcomm Hexagon DSP, now in its fifth generation, is used for both modem processing and multimedia acceleration. By offloading multimedia tasks such as voice, audio, sensor, and image processing from the CPU to the DSP, Hexagon achieves significant power savings. Hexagon features a unique architecture that combines application-specific instructions, a VLIW instruction set architecture, and hardware multithreading. The design approach is to maximize work per cycle for performance, but run at modest clock speeds and focus the implementation on low power. This article provides an overview of the Hexagon architecture. The processor is designed to deliver far superior energy efficiency compared to mobile CPU alternatives and thereby help achieve long battery life for important mobile applications.
Keywords
digital signal processing chips; instruction sets; multimedia communication; Qualcomm hexagon DSP; VLIW instruction set architecture; application-specific instructions; battery life; energy efficiency; hardware multithreading; heterogeneous computing; image processing; mobile multimedia communications; mobile products; modem processing; multimedia acceleration; offloading multimedia tasks; Computer architecture; Digital signal processing; Instruction sets; Multimedia communication; Program processors; Hexagon DSP; digital signal processor; instruction set architecture; multimedia;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/MM.2014.12
Filename
6762801
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