Title :
Sizing consideration for leakage control transistor
Author :
Farbiz, F. ; Farazian, M. ; Emadi, M. ; Sadeghi, K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
Abstract :
In this paper, we report the use of the Genetic Algorithm (GA) to determine the optimum size of the leakage control transistor for low power applications. In the optimization, the energy-delay product is minimized. The transistor is modeled by a neural network to increase the speed and the accuracy of the calculations.
Keywords :
circuit optimisation; genetic algorithms; leakage currents; low-power electronics; multilayer perceptrons; transistors; energy delay product; genetic algorithms; leakage control transistor; low-power electronics; neural network; optimization; Automatic control; Circuit simulation; Delay; Iterative algorithms; Leakage current; Neural networks; SPICE; Threshold voltage; Transistors; Very large scale integration;
Conference_Titel :
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN :
0-7695-2072-3
DOI :
10.1109/ICVD.2004.1260992
