DocumentCode :
2511918
Title :
Constrained floorplanning with whitespace
Author :
Feng, Yan ; Mehta, Dinesh
Author_Institution :
Dept. of Math. & Comput. Sci., Colorado Sch. of Mines, Golden, CO, USA
fYear :
2004
fDate :
2004
Firstpage :
969
Lastpage :
974
Abstract :
This paper considers the constrained floorplanning problem in the context of a design scenario where floor-plans are required to contain some white space to facilitate subsequent buffer insertion. An elegant bounded iterative methodology for floorplan-refinement based on the min-cost max-flow formulation of Feng et al augmented by a heuristic area-redistribution algorithm is presented. This approach results in substantially better quality floorplans than previously reported as substantiated by our experimental results.
Keywords :
circuit layout; circuit optimisation; integrated circuit design; constrained floorplanning; heuristic area-redistribution algorithm; min cost max flow formulation; subsequent buffer insertion; whitespace; Context modeling; Design methodology; Heuristic algorithms; Iterative algorithms; Iterative methods; Shape; Simulated annealing; Very large scale integration; White spaces; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2004. Proceedings. 17th International Conference on
Print_ISBN :
0-7695-2072-3
Type :
conf
DOI :
10.1109/ICVD.2004.1261056
Filename :
1261056
Link To Document :
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