DocumentCode :
2512676
Title :
Package thermal resistance model dependency on equipment design
Author :
Andrews, James A.
Author_Institution :
Motorola Inc., Phoenix, AZ, USA
fYear :
1988
fDate :
10-12 Feb 1988
Firstpage :
122
Lastpage :
129
Abstract :
A physical model is presented that describes mechanisms for operating-equipment junction-to-ambient thermal resistance in excess of a typical component manufacturer´s data-sheet value by as much as a factor of four under constant cooling conditions. The model accounts for the discrepancy between system thermal performance of a package and data-sheet thermal resistance value which are not accompanied by qualifying data in the form of junction-to-header thermal resistance, board temperature rise over ambient, convection coefficient, mounting sensitivity, and power dissipation. The eight constants used to predict inherent increases in package thermal resistance when going from the data-sheet-specified operating conditions to the excess-value conditions are described. These constants and procedures for obtaining them are given for dual in-line packages (DIPs), pin-grid arrays (PGAs), small-outline transistors (SOTs), and plastic leaded chip carriers (PLCCs)
Keywords :
packaging; thermal resistance; board temperature rise; convection coefficient; data-sheet thermal resistance; dual in-line packages; junction-to-ambient thermal resistance; mounting sensitivity; packaging; physical model; pin-grid arrays; plastic leaded chip carriers; power dissipation; small-outline transistors; Cooling; Electronics packaging; Packaging machines; Plastic packaging; Power dissipation; Power system modeling; Temperature sensors; Thermal factors; Thermal resistance; Virtual manufacturing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Thermal and Temperature Measurement Symposium, 1988. SEMI-THERM IV., Fourth Annual IEEE
Conference_Location :
San Diego, CA
Type :
conf
DOI :
10.1109/SEMTHE.1988.10613
Filename :
10613
Link To Document :
بازگشت