DocumentCode :
251354
Title :
Design of DDR4 SDRAM controller
Author :
Islam, M.A. ; Arafath, M. Yeasin ; Hasan, M. Jahid
Author_Institution :
ASIC Design Eng., Fastrack Design Ltd., Bangladesh
fYear :
2014
fDate :
20-22 Dec. 2014
Firstpage :
148
Lastpage :
151
Abstract :
Currently, the demand of memories has been increasing due to its higher speed, lower cost and lower power consumption. The complexity of instructions to control the memory devices increases with the increase in technology. DDR4 is the latest generation family of DDR SDRAM. This memory device provides higher reliability, availability and serviceability than other DDR memories. In this paper, the overall architecture of the DDR4 SDRAM controller is proposed. The detailed design and operation of its individual sub blocks is described. Also the advantages of DDR4 over DDR3 SDRAM are discussed.
Keywords :
DRAM chips; SRAM chips; integrated circuit design; integrated circuit reliability; low-power electronics; power consumption; DDR memories; DDR4 SDRAM controller design; memory devices; power consumption; reliability; Calibration; Clocks; Delays; Pipeline processing; SDRAM; Servers; DDR4; Rank; SDRAM Controller;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Computer Engineering (ICECE), 2014 International Conference on
Conference_Location :
Dhaka
Print_ISBN :
978-1-4799-4167-4
Type :
conf
DOI :
10.1109/ICECE.2014.7026950
Filename :
7026950
Link To Document :
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