Title :
Methodology for ULSI LOCOS isolation built-in reliability analysis
Author :
Loiko, Konstantin V. ; Peidous, Igor V. ; Ho, Hok-Min ; Quek, Elgin K B ; Lim, David H Y
Author_Institution :
R&D Dept., Chartered Semicond. Manuf. Ltd., Singapore
Abstract :
The results of studying the mechanisms of CMOS ULSI LOCOS isolation failures and an effective approach to qualifying the technological processes of isolation manufacturing are presented. The described method for reliability analysis allows one to reveal the potential capability of a current technology
Keywords :
CMOS integrated circuits; ULSI; failure analysis; integrated circuit reliability; isolation technology; masks; CMOS; LOCOS isolation; ULSI; built-in reliability analysis; isolation manufacturing; technological processes; CMOS technology; Degradation; Failure analysis; Isolation technology; Manufacturing processes; Oxidation; Space technology; Testing; Threshold voltage; Ultra large scale integration;
Conference_Titel :
Physical & Failure Analysis of Integrated Circuits, 1997., Proceedings of the 1997 6th International Symposium on
Print_ISBN :
0-7803-3985-1
DOI :
10.1109/IPFA.1997.638065
