Simulation-based assessment of batching heuristics in semiconductor manufacturing

We investigate the performance of different dispatching and scheduling heuristics for batching tools in a semiconductor wafer fabrication facility (wafer fab) by means of discrete event simulation. Because the processing times of lots on batching tools are quite large compared to those of other processes, careful batching decisions may have a great impact on the performance of the entire wafer fab. In a first step, we investigate the performance of certain modifications of the apparent tardiness cost (ATC) dispatching rule that do not take into account future lot arrivals. In a second step, we extend this approach by considering future lot arrivals. In a last step, we combine a genetic algorithm for assignment of the batches to parallel machines with the ATC rule, which takes future lot arrivals into account. We present results of simulation experiments with the different heuristics.