Detailed investigation of geometrical factor for pseudo-MOS transistor technique

The ψ-MOSFET technique offers a plain and quick way to characterize the SOI wafers. We derived a simple relation for the geometrical factor, as a function of probe pressure, silicon island size, and probe spacing. An empirical expression for the modified geometrical factor (f_g´) is proposed. It has been demonstrated that f_g´ produces a reliable extraction of the low-field carrier mobility from I_D-V_G curves in ψ-MOSFETs on advanced SOI substrates.