DocumentCode :
2517130
Title :
Noise improvement of 3–5GHz CMOS UWB LNA with low power consumption
Author :
Li, Chia-Chien ; Yang, Jeng-Rern
Author_Institution :
Dept. of Commun. Eng., Yuan Ze Univ., Jhongli, Taiwan
fYear :
2010
fDate :
12-16 April 2010
Firstpage :
118
Lastpage :
121
Abstract :
A single inductor matching network that carried low noise is designed to achieve the input wideband matching. This way has lower complexity that reduces chip area and holds the good reflection coefficient. Besides, the current reuse technique was used to achieve low power consumption. The design is simulated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.18μm RF CMOS process. Through a 1V/5.56mA supply, the LNA achieved the maximum gain of 16.69dB with gain flatness ± 0.5dB; input return loss lower than -10dB; and a minimum noise figure 2.6dB in 3~5 GHz.
Keywords :
CMOS integrated circuits; low noise amplifiers; CMOS UWB LNA; RF CMOS process; Taiwan Semiconductor Manufacturing Company; current reuse technique; input wideband matching; low power consumption; noise improvement; reflection coefficient; single inductor matching network; Acoustic reflection; Energy consumption; Impedance matching; Inductors; Manufacturing processes; Radio frequency; Semiconductor device manufacture; Semiconductor device noise; Virtual manufacturing; Wideband; LNA; UWB; low power;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electromagnetic Compatibility (APEMC), 2010 Asia-Pacific Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-5621-5
Type :
conf
DOI :
10.1109/APEMC.2010.5475861
Filename :
5475861
Link To Document :
بازگشت