Understanding conductance quantization in thin SOI MOSFET by quantized-energy-level simulation

A device simulator to investigate conductance oscillations in small scale devices is developed. The simulator is applied to analyze measured transconductance g/sub m/ oscillations of a thin silicon-on-insulator (SOI) MOSFET. It is explained that the oscillations are caused by thin Si-layer region in the channel, about 15% thinner, originated by roughness at the interface between the Si and buried SiO/sub 2/. The thinner region affects as a barrier for carriers. Transmission of the carriers at the ground state through the barrier is mainly responsible for the g/sub m/ oscillations in the gate voltage region V/sub G/ above the threshold condition. For larger V/sub G/ values the first-excited state becomes important.