Multi-step counting ADC

A counting analog-to-digital converter (ADC) is proposed which achieves a high sampling rate by performing the conversion in several (N) steps. In terms of the effective number of bits (ENOB) of the ADC, the conversion time of the ADC is approximately N.2^ENOB/N clock periods, which is much shorter than for traditional counting ADCs (2^ENOB clock periods). This is achieved by using novel methods of residue amplification and correlated double sampling. Simulation results are provided to verify the effectiveness of this structure.